Lab 2

Lab #2: VHDL Components

Lab 2 is due Wednesday, March 11. Your lab report and source code must be submitted by 10:10 AM on Wednesday before class. The late policy applies to this lab project.

This lab is to be done in teams. Get started early! Also, remember to put your names on the lab report! The required format for lab reports is shown here.

Problem 1
Develop a behavioral VHDL model for a 4-to-1 word multiplexer (MUX). Your model should work with arbitrary length words; i.e., you should not place hard constraints on the lengths of inputs and outputs. Develop a test bench for your MUX that demonstrates each function for all possible input permutations.

Problem 2
Develop a behavioral VHDL model for a 1-bit, 2-to-4 demultiplexer. Your device should include an ENABLE signal as well as normal inputs and outputs. Develop a test bench for your VHDL demultiplexer model that demonstrates basic functionality. Simulate your design to demonstrate correctness for all possible input permutations.

Problem 3
Develop a behavioral VHDL model for a 4-bit shift register. Your shift register should implement functions for LOAD, HOLD, RIGHT SHIFT and LEFT SHIFT. In addition to regular inputs, your shift register should provide a SHIFT LEFT INPUT and a SHIFT RIGHT INPUT that input the value shifted into the right-most and left- most bits, respectively. Your register should also include an ENABLE input and a CLOCK input. Design your register to be a positive level-triggered device. Develop a test bench for your VHDL shift register that demonstrates each function for all possible combinations of input signals of "I_SHIFT_IN", "sel", "clock", "enable", and at least two values of "I". Here is a sample shift_reg program that only declares the interface. A sample test bench that tests only two input cases is provided here.

Problem 4
Use your 4-bit shift register from Problem 3 to implement a structural VHDL model for an 8-bit shift register. This device should perform the same functions as the 4-bit shift register, but over 8 bits. Develop a test bench for your shift register that demonstrates each function for all possible combinations of input signals of "I_SHIFT_IN", "shift", "clock", "enable", "load", and two values of "I"..

Problem 5
Modify your design from Problem 3 to implement a rising edge triggered device. If you designed your system carefully, this should involve changing exactly one line of VHDL. Modify your test bench from Problem 3 to demonstrate the distinction between the two shift registers. (Hint: you need more than one transaction to show the difference.)

Problem 6
Use your shift register model from Problem 5 and your MUX model from Problem 1 to develop a 4-bit Gray-code counter. Your counter should implement LOAD, HOLD, COUNT UP and COUNT DOWN functions. Your counter should also include an ENABLE input and a CLOCK input. Design your counter to be a rising edge-triggered device. Develop a test bench that test the function of the Gray-code counter.

Use synthesizable features of VHDL

You should try to use only the synthesizable features of VHDL. In particular, only one "wait" statement is allowed in a process. The "wait for" statements are not allowed in your implementation, but might be used in your test benches.

How to test using GHDL

GHDL is installed under the directory /usa/xli/local/bin. The ghdl compiler is for linuxlab.acad.ece.udel.edu only. Assuming we have "shift_reg.vhdl", which is the implementation of a 4-bit shift register, and "shift_reg_tb.vhdl", which is the test bench for our implementation, there are three steps to run the test bench:

(1) Analyze: Compile the two vhdl files
"/usa/xli/local/bin/ghdl -a shift_reg.vhdl"
"/usa/xli/local/bin/ghdl -a shift_reg_tb.vhdl"

(2) Generate the executable for the test bench:
"/usa/xli/local/bin/ghdl -e shift_reg_tb"

(3) Run the test bench:
"/usa/xli/local/bin/ghdl -r shift_reg_tb"

What to Turn In

For this lab project, turn in all of your source code, including the code that implements the components, and the code that tests your implementations. Describe your testing methodology. For problem 3, 4, 5, 6, explain why you select the input values that are used to test your implementation.

How to Submit

Copy your lab report, which is a .pdf, a .doc, or a .html file, and all your source code into an empty directory. Assuming the directory is "submission", make a tar ball of the directory using the following command:

tar czvf [your_first_name]_[your_last_name]_lab2.tar.gz submission.

Replace [your_first_name] and [your_last_name] with your first name and your last name.

/usa/xli/bin/cpeg324_submit lab2 [your_first_name]_[your_last_name]_lab2.tar.gz

The time when you run cpeg324_submit is used as the time-stamp of your submission.

Peer evaluation: Please email your peer evaluation (guideline is here) of your teammates, including scores and justification, directly to xli@ece.udel.edu.