Lab 3

Lab #3: Single-cycle CPU Components

Lab 3 is due Monday, Apr. 6. Your lab report and source code must be submitted by 10:10 AM on Monday before class. The late policy applies to this lab project.

This lab is to be done in teams. Get started early! Also, remember to put your names on the lab report! The required format for lab reports is shown here.

In this project, the size of a word is 32 bits.

Problem 1: Instruction Memory
Develop a read-only instruction memory. The size of the instruction memory is 128 words (512 bytes). The memory is addressed by byte. The address space of the instruction memory is 0x00000000 - 0x000001FF. If the input address is out of range, the data output should all be set to 'U'. Your device should be initialized from a file named "imem" (example here). The "imem" contains 128 lines, which are the hexadecimal representation of the word that stores in the corresponding memory unit. Figure 1 is the block diagram of the instruction memory. Arrows show the direction of ports. The numbers beside arrows are the widths of the ports. Simulate your design to demonstrate that your implementation can read the initialization file , and every word can be addressed and read correctly.

Figure 1: Instruction memory

Problem 2: Data Memory
Develop a read/write data memory. The size of the data memory is 128 words (512 bytes). The memory is addressed by byte. The address space of the data memory is 0x00000200 - 0x000003FF. If the input address is out of range, the data output should all be set to 'U'. Your device should be initialized from a file named "dmem" (example here). The "dmem" contains 128 lines, which are the hexadecimal representation of the word that stores in the corresponding memory unit. Figure 2 is the block diagram of the data memory. Arrows show the direction of ports. The numbers beside arrows are the widths of the ports. Simulate your design to demonstrate that your implementation can read the initialization file , and every word can be addressed, read, and writen correctly.

Figure 2: Data memory

Problem 3: Register File
Develop a behavioral VHDL model for a 32-bit register. Then, using your register implementation, develop a structural model for a register file that has 32 registers (Hint: use "generate" statement). All registers are initialized to zero. The registers are addressed from 0x00 to 0x1f. Register "0" always outputs zero. Figure 3 is the block diagram of the register file. Simulate your design to demonstrate that your register file can address, read, and write every register correctly.

Figure 3: Register file

Problem 4: ALU
Develop a behavioral VHDL model for a 32-bit ALU. The ALU has a 4-bit "op" control singal. The relationship between the "op" and the operations of the ALU is as defined in the table o p. 301 in our textbook. The table is copied below. You should implement all functions in the table. The "Equal" signal must be set 'U' when not used by "op". Figure 4 is the block diagram of the ALU. Develop a test bench that demonstrates your ALU implements all functions correctly.

Figure 4: ALU

ALU control lines	Function
0000	AND
0001	OR
0010	add
0110	subtract
0111	set on less than
1100	NOR

Problem 5: PC and PC adder
Develop two behavioral VHDL models, one for the program counter (PC), and the other for the adder that add 4 to the current PC value, and select, between the output of the adder and another input, based on a 1-bit control signal. In addition, develop a structural model that connect the PC model and the adder model together. The block diagram of the components is shown in Figure 5. You must test your implementation with all permutations of the control signals, and demonstrate that your PC can increment, write from both the adder and the other source, and read correctly.

Figure 5: PC and PC adder

Problem 6: Sign Extend
Design a VHDL model that sign extends a 16-bit number to a 32-bit number. You must test your implementation with at least two input cases.

Problem 7: Shift Left 2
Design a VHDL model that left shift a 32-bit number by 2 bits. You must test your implementation with at least two input cases.

How to test using GHDL

GHDL is installed under the directory /usa/xli/local/bin. The ghdl compiler is for linuxlab.acad.ece.udel.edu only. Assuming we have "shift_reg.vhdl", which is the implementation of a 4-bit shift register, and "shift_reg_tb.vhdl", which is the test bench for our implementation, there are three steps to run the test bench:

(1) Analyze: Compile the two vhdl files
"/usa/xli/local/bin/ghdl -a shift_reg.vhdl"
"/usa/xli/local/bin/ghdl -a shift_reg_tb.vhdl"

If you use any IEEE libraries, add "--ieee=synopsys" after "-a".

(2) Generate the executable for the test bench
"/usa/xli/local/bin/ghdl -e shift_reg_tb"

If you use any IEEE libraries, add "--ieee=synopsys" after "-e".

(3) Run the test bench:
"/usa/xli/local/bin/ghdl -r shift_reg_tb"

What to Turn In

For this lab project, turn in all of your source code, including the code that implements the components, and the code that tests your implementations. Describe the testing methodology. For problem 3, 4, 5, 6, explain why you select the input values that are used to test your implementation.

How to Submit

Copy your lab report, which is a .pdf, a .doc, or a .html file, and all your source code into an empty directory. Assuming the directory is "submission", make a tar ball of the directory using the following command:

tar czvf [your_first_name]_[your_last_name]_lab3.tar.gz submission.

Replace [your_first_name] and [your_last_name] with your first name and your last name.

/usa/xli/bin/cpeg324_submit lab3 [your_first_name]_[your_last_name]_lab3.tar.gz

The time when you run cpeg324_submit is used as the time-stamp of your submission.

Peer evaluation: Please email your peer evaluation (guideline is here) of your teammates, including scores and justification, directly to xli@ece.udel.edu.