Lab #6: Pipeline CPU Data-path and Controller

Lab 6 is optional and is due Friday, May 22. Your lab report and source code must be submitted by 11:59 PM on Friday. The late policy applies to this lab project.

You can substitute the final exam with Lab 6. Because Lab 6 is more demanding, a higher weight (20%) of your Lab 6 grade will be assigned toward your overal score. If you choose to do both, the following fomula will be used max(lab6*0.2, final*0.15).

This lab is to be done in teams. Get started early! Also, remember to put your names on the lab report! The required format for lab reports is shown here.

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In this project, the size of a word is 32 bits.

In this project, you will design and build your own pipeline MIPS processor. Your pipeline processor only need to support two instructions, ADD and SW, and only need to support data forwarding between ADD instructions.

Your task in this lab will be to modify the multi-cycle datapath from Lab 5 to build a pipeline datapath(Problem 1), design and test a implementation for the pipeline controller (Problem 2), to merge your controller with your pipeline datapath to build a complete processor, and to work out a test program for the processor as a whole (Problem 3). You may reuse any of your designs and implementations from previous labs.

Problem 1: Pipeline Datapath

You need to make two major modifications to your multi-cycle datapath to build a pipeline datapath. The first modification is the addition of inter-stage registers. The inter-stage registers need to store both the instruction word or the control signals, and the data that will be used by the remaining stages of the current instruction. The other modification is the addition of data forwarding paths. Because we only need to implement data forwarding between ADD instructions, we only need to add the following two paths (1) From the inter-stage data register between stages 3 and 4 to the two ALU input port multiplexers, and (2) From the inter-stage data register between stage 4 and 5 to the two ALU input port multiplexers. The control singals for the two ALU input port multiplexers need to be expanded. What we mean to implement data forwarding in this lab is really how to set the values for the two expanded ALU input port control signals correctly.

Problem 2: Pipeline Datapath Controller

The controller is the most complex part of the pipeline processor. The biggest difference between a pipeline controller and a multi-cycle controller is that you need to set the controll signals in stages (you can't set all control singals in one-shot.) and you need to consider two previous instructions to determine whether to do data-forwarding or not, which is implemented by setting the two ALU input port control signals.

The overall controller interface of inputs and outputs is defined as the table below. To simplify your task, you can use a behavior model for the implementation of the controller.

Contoller Interface

Control Signal	Width	Input/Output	Control Signal	Width	Input/Output
CLK	(0:0)	Input	REGWRITE	(0:0)	Output
RESET	(0:0)	Input	REGDST	(0:0)	Output
OP of Current Inst.	(5:0)	Input	IORD	(0:0)	Output
FUNCT of Current Inst.	(3:0)	Input	MEMREAD	(0:0)	Output
RS's of Current Instructions	(4:0)	Input	MEMWRITE	(0:0)	Output
RT's of Current Instructions	(4:0)	Input	MEMTOREG	(0:0)	Output
RD's of Previous 2 Instructions	(9:0)	Input	IRWRITE	(0:0)	Output
ZERO	(0:0)	Input	PCENABLE	(0:0)	Output
PCSOURCE	(1:0)	Output
ALUCONTROL	(3:0)	Output
ALUSRCB	(2:0)	Output (data forwarding)
ALUSRCA	(1:0)	Output (data forwarding)

Problem 3: Pipeline Datapath Completion and Test

The last step is to connect your pipeline controller with your pipeline datapath. There is nothing special here and we don't need implement additional major components. Just pay attention that we still have a register file that is dual-activated in the same cycle, and we still use a RESET signal for all flip-flops. The specification of the two components are copied below from Lab 5:

There is an important issue related to the dual-port register file that can be read/writen in the same cycle. One trick to allow both writing and reading properly is to let the reading operation be done at the falling edge of the clock instead of the rising edge. This way, the reading address comes from the correct instruction, which is only valid until slightly after the clock rising edge.

You can copy additional function units, such as the ALU, from previous labs. Finally, when you have finished all components, connect them together in a top-level schematic. The design should only take CLK and RESET as inputs. All of your flip-flops should take a RESET input to reset the initial value to a known state. The Instruction Register and PC also require CLK_EN enable inputs. Pay careful attention to bus connections; they are an easy place to make mistakes.

Test bench for your implementation:

Because Lab 6 only supports ADD and SW, you should re-design of your test program. Your test program should only use ADD and SW instructions and should contain more than 5 instructions to show that all stages of your pipeline datapath work properly. Furthermore, your test program should test the activation of both data-forwarding paths. Because we only support data-forwarding between ADD's, you should make sure that the three instructions before any SW instruction must be independent to the SW to ensure the correctness of your program. Be sure to enter your test program into the content of the memory RAM. Feed your pipeline processor implementation with clock signals from your VHDL test-bench until the completion of the program. You should expect the same output as that of running the same test program with your Lab 5 implementation , though different number of cycles are needed to finish the same test program. Check that your results match the expectations .

How to run MIPS test programs in your VHDL CPU model?

A sample MIPS test program, test.asm, is provided here. In addition, you can find a MIPS assembler at "/usa/xli/local/bin/mipsasm". You can load a test program by first generating the binary code for the MIPS assembly program, and rename the binary code to "imem". Remember in Lab 4 that your implementation of the instruction memory should read from the file "imem" to initialized the 128 memory lines. Also initialize the PC to be zero. As a result, at the first clock rising edge, your CPU model should start executing the first instruction at address 0, the starting address of the combined memory. The command line of mipsasm is "/usa/xli/local/bin/mipsasm test.asm imem".

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