The 22nd International Workshop on Languages and Compilers for Parallel Computing

Trabant University Center, University of Delaware, Newark, Delaware, USA. October 8-10, 2009

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Keynote Speakers


Keynote I: HPC in Phase Change: Towards a New Parallel Execution Model

Thomas Sterling
Professor of Computer Science
Center for Computation & Technology
Department of Computer Science
Louisiana State University

Abstract: Since 2007, high performance computing has been at the beginnings of
the most dramatic change in form and function in the last decade and a half. Since
the advent of the killer micro and the MPPs and commodity Clusters it spawned
supported by message-passing programming techniques, most notably MPI, HPC
has been on an exponential curve augmenting performance at historic rates through
incremental changes to feature size, clock rate, and architectural complexity. But
as always happens with S-curves, HPC is turning towards its final asymptote and
is undergoing what may prove to be its 6th and potential final phase change. Most
visible is the adoption of multicore heterogeneous system architectures driven by
constraints in power, complexity, clock rate, and reliability while continuing to
exploit improvements in feature size to achieve growth in performance. To realize
this goal and the achievement of Exascale performance by the end of the next decade
within practical limitations critical advances in efficiency, scalability, energy, and
programmability will be required. In all previous such metamorphoses in HPC, the
underlying principles of a new execution model was used to guide the co-design of
new architectures, programming methods, and system software. Such is the case for
the emerging HPC Phase VI. This presentation will discuss the likely elements the
new execution model based on the exploratory ParalleX model of computation, and
describe key attributes of architecture, operating, and runtime system software, and
programming methods that are likely to gain ascendency over the next decade.
Results from recent experiments with HPX prototype runtime system will be presented.


Keynote II: The Polytope Model, Past, Present, Future

Paul Feautrier
Professor
Ecole Normale Supérieure de Lyon, France

Abstract: The polytope model resulted, around 1990, of the conjunction of the
Systolic Array Design community and the Automatic Parallelization
community. At the time, both communities where toying with program
transformations, and it was soon realized that applying transformations
at the abstract level of the Iteration Space was much easier than
transforming the program text. Since then, the model has been applied
to scheduling, vectorization, distribution, and memory and locality
optimization.

The model has two drawbacks: the severe restrictions it imposes on
the source program, and its lack of scalability. I will sketch
some research directions toward the resolution of these difficulties.


Keynote III: The Soul of A New Language: The Story of UPC

Bill Carlson
IDA Center for Computing Sciences